How is MSM waked up from deep sleep (TCXO shutdown)?

Here, the description applies to MSM with MPM (MAO) block. When MSM is in deep sleep (TCXO shutdown), the CPU is put in SWFI (Stop and Wait For Interrupt) state, it needs a hardware interrupt to trigger the CPU into running again. Since the regular interrupt controller is disabled, and only the interrupt controller in MPM (MAO) block is active. Therefore, only interrupts described in maoint_isr_type can bring MSM out of sleep. Here are some descriptions of these interrupts.

1) MAO_WAKEUP_ISR: this interrupt is generated when a timer in MPM block expires. This is used to wake up MSM when the prescribed sleep time has expired. So you may think that MSM is waked up by MPM timer, whose expiration time is calculated and set by the sleep_task before entering sleep. Generally, such sleep time is determined by RF slot cycle and the next expiring software timers.
2) Special interrupts such as MAO_TOUCH_SCREEN_ISR and MAO_USB_HS_ISR: these interrupts are generated by the specific modules' hardware controllers (for instance, touch screen controller and USB controller).
3) GPIO interrupts: these interrupts are generated by specific GPIOs whose interrupts are enabled when the triggering condition is met.
4) PM_INT: PMIC uses one of the GPIO interrupts, which is wakeup capable, to interrupt MSM. In addition, PMIC has its own interrupt subsystem. Therefore, many PMIC interrupts (e.g. Wall charger, power key) that are handled by PMIC can wake up MSM through the PMIC GPIO pin. In other words, from MSM's perpective, all these PMIC interrupts are muxed together to wake up MSM through PMIC GPIO.

The wakeup GPIOs are generally fixed for each MSM. However, they can be completely different in different MSMs (for instance, QSD8650 and MSM7200A). As a initial step of board design, hardware engineers need to review the MSM GPIO assignment. One of the steps in GPIO assignment review is to see what pins are used as wakeup pins in the design, and make sure that the assigned GPIO pins have wakeup capability.

Instead of TCXO_EN, can any GPIO be used for controlling USB clock buffer (NAND gate)?

Question :

As seeing Reference schematic for all the MSMs which are supporting HS-USB by using internal HS-USB PHY circuit, TCXO_EN signal is used for enable signal of NAND gate for USB clock. But USB clock is usually not required when USB block is not operating without USB cable inserted.

So to reduce leakage current on this NAND gate and control USB clock properly at this case, can any GPIO instead of TCXO_EN be used for enable signal of this NAND gate?



Answer :

No. TCXO_EN should be used for this. Basically, USB clock should be supplied during normal operation even when USB is not operating including suspend mode, in order to meet USB 2.0 specification requirement for HS-USB enumeration time.

In addition, in case of using normal GPIO, sleep current actually increases to more than 1mA from both VREG_MSMC & VREG_MSMA due to feedback nature of the external NAND circuit when TCXO was no longer supplied.

MSM7x30 BL/LCD Power Measurement Procedure

1. In order to measure LCD and BL on Spartanized FFA, need SW and HW tools: UDAS application, Spartan station, SIC3 card or LowRider card, shorting blocks.
2. Follow the video test precedure ans select the folling power grid (as below) from UDAS channel list and do the measurement.
3. On 7x30 LPDDR1 Spartanized FFA: Total BL/LCD = 156mA.
SET1-2D:MEdia_1E_MDDI=25.72mA
SET1-7C:LCD_3d05V=8.93mA
SET2-0C:Media_VDDS_MDDI_LCD=8.35mA
SET2-6D:Media_eDRAM_VDD2E=2.54mA
SET2-4A:KYPD_BL=0mA
SET2-5D:LCD_BL=110.14mA

MSM7x30 MP3 Power Measurement Procedure

1. After loading the build, load the QCN for the phone and make sure phone is camped on the network (WCDMA usually used internally). Load the MP3 file, plug in headset and reset the phone.
2. Set the screen timeout to "15 seconds"
3. Skip this step if the regular FFA is used for measuring
- Make sure Class D configuration is enabled if Spartanized FFA is being used for measurements
a. Connect the USB
b. Run HeadsetConfig_7x30_DLegacy.bat script to configure Class D, make sure no error mssage
c. Playback MP3 file
d. Unplug USB
4. Headset Calibration @ .1mW(for both Spartanized and non-Spartanized FFAs)
- When the file starts playing, adjust the volume button on the left side of the FFA to mute and then increase volume 4 times from mute.
- Customer need to ensure headset output .1mW on their device.
5. For MP3, wait for LCD/BL off, then start power measurement

PM8058 Voltage Regulator Hardware-to-Software Mapping Guide

Table provides a cross-reference for PM8058 voltage regulator names in hardware and software.

VREG	SW ID	Type	I-rated (mA)	Default Vout (V)	Default state	Programmable range (V)
S0	VREG_MSMC1	Buck SMPS	1500	1.1	On	0.375 � 3.050
S1	VREG_MSMC2	Buck SMPS	1500	1.1	On	0.375 � 3.050
S2	VREG_RF1	Buck SMPS	1500	1.35	Off	0.375 � 3.050
S3	VREG_MSME	Buck SMPS	1500	1.8	On	0.375 � 3.050
S4	VREG_RF2	Buck SMPS	1500	2.2	Off	0.375 � 3.050
NCP	VREG_NCP	Charge pump	200	-1.8	Off	-3.050 � -1.800
L0	VREG_GP3	Linear n LDO	150	1.2	On	0.750 � 1.525
L1	VREG_GP8	Linear n LDO	300	1.2	On	0.750 � 1.525
L2	VREG_XO_OUT_D0	Linear p LDO	300	2.6	On	1.500 � 3.050
L3	VREG_USIM	Linear p LDO	150	1.8	On	1.500 � 3.050
L4	VREG_TCXO	Linear p LDO	50	2.85	On	1.500 � 3.050
L5	VREG_SDCC1	Linear p LDO	300	2.85	On	1.500 � 3.050
L6	VREG_USB_3P3	Linear p LDO	50	3.075	On	3.075
L7	VREG_USB_1P8	Linear p LDO	50	1.8	On	1.500 � 3.050
L8	VREG_GP7	Linear p LDO	300	2.2	Off	1.500 � 3.050
L9	VREG_GP1	Linear p LDO	300	2.05	Off	1.500 � 3.050
L10	VREG_GP4	Linear p LDO	300	2.6	Off	1.500 � 3.050
L11	VREG_GP2	Linear p LDO	150	2.8	Off	1.500 � 3.050
L12	VREG_GP9	Linear p LDO	150	2.9	Off	1.500 � 3.050
L13	VREG_WLAN1	Linear p LDO	300	2.85	Off	1.500 � 3.050
L14	VREG_RF	Linear p LDO	300	2.85	Off	1.500 � 3.050
L15	VREG_GP6	Linear p LDO	300	2.85	Off	1.500 � 3.050
L16	VREG_GP10	Linear p LDO	300	1.8	Off	1.500 � 3.050
L17	VREG_GP11	Linear p LDO	150	2.2	Off	1.500 � 3.050
L18	VREG_GP12	Linear p LDO	150	2.2	Off	1.500 � 3.050
L19	VREG_WLAN2	Linear p LDO	150	2.5	Off	1.500 � 3.050
L20	VREG_GP13	Linear p LDO	150	1.5	Off	1.500 � 3.050
L21	VREG_GP14	Linear n LDO	150	1.1	On	0.750 � 1.525
L22	VREG_GP15	Linear n LDO	300	1.2	Off	0.750 � 1.525
L23	VREG_GP5	Linear n LDO	300	1.2	Off	0.750 � 1.525
L24	VREG_GP16	Linear n LDO	150	1.3	Off	0.750 � 1.525
L25	VREG_GP17	Linear n LDO	150	1.3	Off	0.750 � 1.525
LVS0	VREG_LVSW0	Low voltage switch	100	-	Off	-
LVS1	VREG_LVSW1	Low voltage switch	100	-	Off	-