8960 Android GSBI UART Debug Tips

1.  Check Registration

Run following commands to test if UART is properly registered with TTY stack.

adb shell      ->  Starts a new shell   

ls /dev/ttyHS* ->  lists all the current serial  ports registered with TTY layer.

Low speed UART would be listed as ttyHSL#
High speed UART would be listed as ttyHS#

 

2.  Check Internal Loop-back

Run following commands to test UART block with internal loop back enabled. 

adb shell  
mount -t debugfs none /sys/kernel/debug  -> mount debug file system

cd /sys/kernel/debug/msm_serial_hs  -> for high speed UART
cd /sys/kernel/debug/msm_serial_hsl -> for low speed UART
echo 1 > loopback.# -> Enable loop back. 
cat loopback.#      -> To verify loop back is enabled.

 

Open another cmd window and type following command to print UART RX Data
adb shell         
cat /dev/ttyHS#    -> if you're testing High speed UART
cat /dev/ttyHSL#  -> if you're testing Low speed UART

 

Go back to first shell and type following cmd to transmit test data
echo "Testing Low Speed UART" > /dev/ttyHS#  -> If you're testing high speed UART

echo "Testing High Speed UART" > /dev/ttyHSL#   -> If you're testing low speed UART

If the echo completes immediately and loop back works then you can safely assume UART block and DMA configuration are set up properly (Only need to verify GPIO related configurations).

 

Following section describe some of key registers that needs to be verified in case UART is not working properly. After attaching debugger to Krait core, user can use command D AZ:PhysicalAddress to get the register readings.  Also all the physical addresses listed below are for information only.  Please refer to software interface manual for latest physical address and bit settings information.

3.  ADM related registers

Following registers used to select between QUP or UART
0x1A400070  = TCSR_ADM_0_A_CRCI_MUX_SEL
0x1A400074  = TCSR_ADM_0_A_CRCI_MUX_SEL

Following register select primarily or secondary device (CRCIn_MUX_SEL) and
correct block size (CRCIn_BLOCK_SIZE).
0x18300400 + 4 * (n) = ADM3_0_HI_CRCIn_CTL_SD0 where n is the CRCI number
For example:
0x18300404 = ADM3_0_HI_CRCI1_CTL_SD0
0x18300408 = ADM3_0_HI_CRCI2_CTL_SD0

Make sure to set following bits on following clock register before accessing
above registers:

0x00903080 = SC0_U_CLK_BRANCH_ENA_VOTE [Set Bit #2 and Bit #3]

4.  GSBI CTRL Registers

Make sure GSBIn_HCLK_CTL[4] is set before accessing below GSBI registers
0x009029C0 + ( 32 * (n - 1 ) ) = GSBIn_HCLK_CTL
For example:
0x009029C0 = GSBI1_HCLK_CTL
0x009029E0 = GSBI2_HCLK_CTL

Check to make sure GSBI CTRL REG[PROTOCOL CODE] is set properly.
0x16000000 = GSBI1_CTRL_REG
0x16100000 = GSBI2_CTRL_REG
0x16200000 = GSBI3_CTRL_REG
0x16300000 = GSBI4_CTRL_REG
0x16400000 = GSBI5_CTRL_REG
0x16500000 = GSBI6_CTRL_REG
0x16600000 = GSBI7_CTRL_REG
0x1A000000 = GSBI8_CTRL_REG
0x1A100000 = GSBI9_CTRL_REG
0x1A200000 = GSBI10_CTRL_REG
0x12440000 = GSBI11_CTRL_REG
0x12480000 = GSBI12_CTRL_REG

5.  GPIO_CFGn Registers

Check to make sure FUNC_SEL is set to GSBI, and GPIO_PULL is set to No Pull ("00")
0x00801000 + 0x10(n) = GPIO_CFGn
For Example:
0x00801000 = GPIO_CFG0
0x00801010 = GPIO_CFG1