How to modify drive strength driven by LPDDR2 device on M8660 target ?

The default DDR driver of M8660 target doesn't provide MR3 therefore the reset default setting of MR3 which is typically 40ohm is used in LPDDR2 device.
                   If need to adjust DS of memory device, the following will help.

Details: If DS is too strong, plz set a bigger R for mr_wdata. Otherwise a less R would help to get a higher DS.

\modem_proc\core\boot\ddr\hal\target\msm8660\src\HAL_BOOT_DDR.c
void HAL_SDRAM_Update_MR_Settings(SDRAM_INTERFACE interface_name, SDRAM_CHIPSELECT chip_select)
<at the end of this function>

  /* configure MR3 only for EBI1 */
  if(interface_name == SDRAM_INTERFACE_1)
  {
    /*
      Configure the I/O Configuration 3 Mode Register in the LPDDR2 device using the following
      sequence. This sets attributes like read and write latency.
      MR3
      // DS Write-only OP<3:0>
      // 0000B: reserved
      // 0001B: 34.3-ohm typical
      // 0010B: 40-ohm typical (default)
      // 0011B: 48-ohm typical
      // 0100B: 60-ohm typical
      // 0101B: reserved for 68.6-ohm typical
      // 0110B: 80-ohm typical
      // 0111B: 120-ohm typical (optional)
      // All others: reserved
    */
    /* Set to MR3 */
    BOOT_HWIO_OUTM(EBI1_CH0_DDR_MR_CNTL_WDATA, offset,
              HWIO_FMSK(EBI1_CH0_DDR_MR_CNTL_WDATA, MR_ADDR),
              0x3 << HWIO_SHFT(EBI1_CH0_DDR_MR_CNTL_WDATA, MR_ADDR));
   
   /* a smaller RON, a stronger DS and a bigger ROM, a weaker DS */
    mr_wdata = 0x1;
   
    /* write the wdata to register */
    BOOT_HWIO_OUTM(EBI1_CH0_DDR_MR_CNTL_WDATA, offset, HWIO_FMSK(EBI1_CH0_DDR_MR_CNTL_WDATA, MR_WDATA), mr_wdata);
   
    /*
      Set the field "MRW" in DDR_MR_CNTL_WDATA to indicate that this is a mode register
      write command.
      This also triggers the actual write.
    */
    BOOT_HWIO_OUTM(EBI1_CH0_DDR_MR_CNTL_WDATA, offset,
             HWIO_FMSK(EBI1_CH0_DDR_MR_CNTL_WDATA, MRW),
             HWIO_FMSK(EBI1_CH0_DDR_MR_CNTL_WDATA, MRW));
   
    /* Poll for Mode Register Write Complete */
    while(BOOT_HWIO_INM(EBI1_CH0_DDR_MR_CNTL_WDATA, offset, HWIO_FMSK(EBI1_CH0_DDR_MR_CNTL_WDATA, MRW)))
    {}
   
    /* Wait at least 5 DDR1x Clock Cycles*/
    HAL_SDRAM_DDR_Wait(5, 0);
  }