SDRAM wait states customization for Hynix DDR SDRAM on various MSM7K devices

clkrgm_msm.c or clkrgm_mpss_sdram_7627.c

void clk_regime_sdram_init (void)
{
<snip>

    if (tRAS > 7)
    {
      tRAS = 7;
    }

   /*------------------------------------------------------------------------------------------------------*/

   /* Hynix Special Requirement for tDAL, tWR, and tRP */ 
   /* Minimum 3CLK of tDAL(= tWR+tRP) is required because it need minimum 2CLK for tWR and minimum 1CLK for tRP */
   /* Refer to Hynix datasheet */
    if (tWR < 1)
    {
      tWR = 1;
    }
    tDAL = tWR + tRP +1 ;  

   /*------------------------------------------------------------------------------------------------------*/

    clkrgm_mpss_sdram_cfg[i].ebi_sdram_mem_device_parameter_cfg1 =
      HWIO_FVAL(EBI_SDRAM_MEM_DEVICE_PARAMETER_CFG1, TRFC, 
        (tRFC>=16? tRFC-16 : tRFC)) |
      HWIO_FVAL(EBI_SDRAM_MEM_DEVICE_PARAMETER_CFG1, TRP, tRP)   |
      HWIO_FVAL(EBI_SDRAM_MEM_DEVICE_PARAMETER_CFG1, TRAS, tRAS) |
      HWIO_FVAL(EBI_SDRAM_MEM_DEVICE_PARAMETER_CFG1, TRC, tRC)   |
      HWIO_FVAL(EBI_SDRAM_MEM_DEVICE_PARAMETER_CFG1, TMRD, tMRD);
<snip>

 

Without this various symptoms such as reset or lock-up might be observed when Hynix (or Elpida) DDR device applied at clock switching scenario.