Do MSM7630/8655 DDR ctlr issue 'ZQ initialization' (MRW10) to LPDDR2 during init sequence?

Yes. MSM8655-0 DDR controller configure 'ZQ initialization' (MRW10) as part of "hardware ddr init". "hardware ddr init" is hardware triggered DDR initialization which can be trigger by writing bit 0 of EBI0_SDRAM_INIT_CTRL.

In HAL_BOOT_DDR.c, one can see the below part. This is just one register write, but internally DDR ctlr issue 'ZQ initialization' to DDR2 device.
One of requirements is to send MR1/2 after "ZQ initialization". That can be also confirmed in HAL_BOOT_DDR.c, because MR1/2 are configured after the below code line in HAL_BOOT_DDR.c.


HAL_SDRAM_HW_Init()
{
 < code snippet >

/* Trigger the Hardware Initialization flow. */
BOOT_HWIO_OUT(EBI0_SDRAM_INIT_CTRL, offset, 0x0001);

}

The below is the reference from DDR controller design document. The same can be found from LPDDR2 datasheet too.

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ZQ Calibration:
After tINIT5, an MRW ZQ Initialization Calibration command may be issued to the memory
(MR10). For LPDDR2 devices which do not support the ZQ Calibration command, this
command shall be ignored. This command is used to calibrate the LPDDR2 output drivers
(RON) over process, voltage, and temperature. In systems in which more than one LPDDR2
device exists on the same bus, the controller must not overlap ZQ Calibration commands. The
device is ready for normal operation after tZQINIT.
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