How to enable EBI1 Turbo mode (450/492Mhz) on Msm8960 V2.

How to enable EBI1 Turbo mode (450/492Mhz) on M8960 V2.



M8960 V1/V2/V3 provides different clock plan as shown in 80-N6794-1_B_MSM8960_Clock_Plan.

Even though "Issue 14 LPDDR2/EBI/application fabric speed limitation" on V1 described in 80-N1622-4_MSM8960_Device_Revision_Guide has been fixed on V2,

the current software release has not enabled the higher speed operation on V2 and the clock frequency plan can only do 400 MHz on V2.

But this software implementation doesn't reflect MSM8960 V2 HW limitation but is based on the use of 400Mhz LPDDR2 memory devices on MTP8960 and CDP8960.

Since release 1021100, M8960 V3 clock frequency plan has been released and incorporated with the DDR driver update designated up to 492Mhz operation.

As M8960 V2 has been verified with 492Mhz clock frequency, which is the maximum clock speed in V3 clock plan, customer is able to run V2 with 450/492Mhz and this solution introduces how to customize the software release.



Note. This applies only for M8960 V2 along with build 1021100 or beyond.

Note. The EBI1 clock starts from 400Mhz in SBL2 and becomes bumped up to 450Mhz/492Mhz with RPM running as the bus gets requested.



1. Change in Bootloader build



M8960AAAAANAZB1021100\boot_images\core\boot\ddr/hal/target/msm8960/src/HAL_BOOT_DDR.c

void HAL_SDRAM_Init(SDRAM_INTERFACE interface_name, uint32 clk_speed)

/*

For 8960 V3 hardware we support up to 533Mhz,

need to update read write latency to 7/4 instead

*V3 version ID is 0x4

*/

if(HWIO_INM(HW_REVISION_NUMBER, HWIO_FMSK(HW_REVISION_NUMBER, VERSION_ID)) >>

HWIO_SHFT(HW_REVISION_NUMBER, VERSION_ID) >= 0x4)

{

/* V3 or above, update timing for 533Mhz operation */

if(interface_name == SDRAM_INTERFACE_0)

{

HALddr_SDRAM_0_parameters->tRL = 7;

HALddr_SDRAM_0_parameters->tWL = 4;

}

else

{

HALddr_SDRAM_1_parameters->tRL = 7;

HALddr_SDRAM_1_parameters->tWL = 4;

}



BOOT_HWIO_OUTM(DDR_ADDR(TOP_MISC_CNTL), offset,

HWIO_FMSK(DDR_ADDR(TOP_MISC_CNTL), MODE_CLKON_DDR_2X),

1 << HWIO_SHFT(DDR_ADDR(TOP_MISC_CNTL), MODE_CLKON_DDR_2X));

}



As VERSION_ID of V2 is 2, need to modify VERSION_ID check from '4' to '2' as shown below.

--- HWIO_SHFT(HW_REVISION_NUMBER, VERSION_ID) >= 0x4)

+++ HWIO_SHFT(HW_REVISION_NUMBER, VERSION_ID) >= 0x2)





2. Change in RPM build



M8960AAAAANAZR1021100\rpm_proc\core\systemdrivers\clkregim\/src/proc/rpm/8960/clkrgm_rpm_bsp.c

boolean clk_regime_bsp_init (void)

<snippet>

if ( (HWIO_INF(HW_REVISION_NUMBER, VERSION_ID) == 2) ||

(HWIO_INF(HW_REVISION_NUMBER, VERSION_ID) == 4) )

{



clkrgm_rpm_bsp = &clkrgm_rpm_bsp_data_v2;



/* V3 frequency plan. Single rank only. */

if (HWIO_INF(HW_REVISION_NUMBER, VERSION_ID) == 4)

{

/* 8x27: Limit AFAB and DDR to 400MHz */

if ( (HWIO_INF(HW_REVISION_NUMBER, PARTNUM) == 0x07C0) ||

(HWIO_INF(HW_REVISION_NUMBER, PARTNUM) == 0x07D0) ||

(HWIO_INF(HW_REVISION_NUMBER, PARTNUM) == 0x07D1) )

{

clkrgm_rpm_bsp->appsfab.max = CLKRGM_FABRIC_PERF_LEVEL_6;

}

else

{

/* EBI1 Turbo mode */

clkrgm_rpm_bsp->ebi1.max = CLKRGM_EBI1_PERF_LEVEL_7;

}

}



}



** CLKRGM_EBI1_PERF_LEVEL_7 is needed for V2 in order to enable V3 clock plan so plz update as shown below.

/* V3 frequency plan. Single rank only. */

--- if (HWIO_INF(HW_REVISION_NUMBER, VERSION_ID) == 4)

+++ if (HWIO_INF(HW_REVISION_NUMBER, VERSION_ID) >= 2)





3. This solution implies SVS disablement therefore needs the following script when Android completes booting up.



mount �t debugfs none /sys/kernel/debug

cd /sys/kernel/debug/msm-bus-dbg

cd shell-client

echo 1 > mas

echo 512 > slv

echo 3936000000 > ib

echo 1 > update_request



Here, mas is Master, 1 is APP_M0.

Slv is slave , 512 is EBI_CH0

Bus width AFAB/SFAB 8 bytes MMFAB 16bytes

Instantaneous bandwidth (Ib): Reflects how fast the bus needs to be running to accommodate peak data to meet deadlines or avoid stalling a processor

Arbitrated bandwidth (Ab): Reflects the average data throughput requirements, normally Ab is about 0.6*ib.

bus_clock = MAX( SUM(Ab), MAX (Ib) ) / (bus width)

So here EBI connects to AFAB, so 3936000000/8 =492Mhz