How to extend the memory region for A5 use when applying 256MB SDRAM memory device on MDM9x15 LE build

The typical SDRAM memory size on MDM9x15 is 128MB and the default 128MB memory layout of MDM9x15 LE build is :



Name Start End Size (MB)

LPASS 0x46F00000 0x48000000 17

Extension 0x45800000 0x46F00000 23

Q6SW 0x41800000 0x45800000 64

HSUSB 0x41700000 0x41800000 1

A5 0x40800000 0x41700000 15

Q6FW 0x40200000 0x40800000 6

SBL2 0x40100000 0x40200000 1

SMEM 0x40000000 0x40100000 1

Total 128



Note : "A5" in 15MB is a dedicated ram partition only for A5 LE and "Extension" in 23MB is shared with A5 and/or Q6 SW for OEM use, software applications, and miscellaneous Linux drivers.

Note : 128MB is located in 0x4000.0000―0x4800.0000-1.

Note : 256MB is in 0x4000.0000―0x5000.0000-1 if applied.



If desired to extend A5 for more Linux applications and applied 256MB SDRAM memory device, the simplest way is to make use of the extended SDRAM region within 0x4800.0000―0x5000.0000-1 in A5 only and here is how to make.



1. to modify the memory density setting in DDR controller perspective.

boot_images\core\boot\ddr\hw\mdm9x15\ddr_devices.c if using a build before than Meta M9615ACETRMAZD1015,

static HALddr_device_params ddr_device_table[] =

13 , /* num_rows_cs0 */ << change this to 14 .

10, /* num_cols_cs0 */

4, /* num_banks_cs0 */



boot_images\core\boot\secboot3\scripts\9x15_cdp_jedec_lpddr1_1_die.xml if using Meta M9615ACETRMAZD1015 or upward,

Plz refer to chapter 5 in 80-N1218-1_DDR SDRAM HAL APIS AND CUSTOMIZATION REFERENCE GUIDE.

Plz update this sample .xml with the given number of row as shown above, generate boot_cdt_array.c, place it in boot_images\core\boot\secboot3\hw\mdm9x15, and rebuild SBL1 again.






2. to modify the memory region definition such as the base address of each ram partitions in SW perspective.

apps_proc\bootable\bootloader\lk\target\mdm9615\atags.c



#define SIZE_128M (16 * SIZE_8M) // add this macro.



unsigned *target_atag_mem(unsigned *ptr)

<snip>

if (smem_ram_ptable_init(&ram_ptable)) {

for (i = 0; i < ram_ptable.len; i++) {

if (ram_ptable.parts[i].category == SDRAM &&

ram_ptable.parts[i].type == SYS_MEMORY &&

ram_ptable.parts[i].start == 0x40000000) {

ASSERT(ram_ptable.parts[i].size >= SIZE_15M);



*ptr++ = 4;

*ptr++ = 0x54410002;

*ptr++ = SIZE_15M;

*ptr++ = ram_ptable.parts[i].start + SIZE_8M;



*ptr++ = 4;

*ptr++ = 0x54410002;

*ptr++ = SIZE_23M; << change this to SIZE_128M.

*ptr++ = ram_ptable.parts[i].start + SIZE_88M; << change this toSIZE_128M.



}

}

<snip>



unsigned target_get_max_flash_size(void)

{

return (SIZE_23M); << change this to SIZE_128M.

}